common #define through all header files and libraries

[StudentFS]

Sorry for stupid question, I am a newbie in makefiles and libraries. I have a bunch of implementation *.cc files in source folder and a bunch of header files *.h and libraries *.templates.h in include folder. In the makefile I have

cc-files    = $(shell echo source/*.cc)
o-files     = $(cc-files:source/%.cc=lib/$(prm)d/%.$(OBJEXT))
go-files    = $(cc-files:source/%.cc=lib/$(prm)d/%.g.$(OBJEXT))
h-files     = $(wildcard include/*.h)

# While the ChangeMe is remade every time it is missing...
ChangeMe: include/DoNotChangeMe.default
	cp include/DoNotChangeMe.default ChangeMe

Makefile: ChangeMe
	touch Makefile

I have global options A and B which influence all code files above. If I would have one file I would use

#define OPTION A
#if OPTION == A
...
#endif
#if OPTION == B
...
#endif

to choose what code I want. Here in ChangeMe I also can define OPTION =1 or OPTION=2 and then use if(OPTION==1) {...} in the code. But is it possible to go through #define which would exclude compilation of unnecessary code?
Best,
Serg