Sorry, I got my count wrong

Offset 28 is MXCSR_MASK

From the manual page 284:

The denormals-are-zero flag in the MXCSR register is available in most of the Pentium 4 processors and in the Intel
Xeon processor, with the exception of some early steppings. To check for the presence of the DAZ flag in the MXCSR
register, do the following:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.
3. Execute the FXSAVE instruction, using the address of the first byte of the cleared FXSAVE area as a source
operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A, for a description of the FXSAVE instruction and the
layout of the FXSAVE image.
4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28 through 31).
— If the value of the MXCSR_MASK field is 00000000H, the DAZ flag and denormals-are-zero mode are not
supported.
— If the value of the MXCSR_MASK field is non-zero and bit 6 is set, the DAZ flag and denormals-are-zero
mode are supported.
This is what mxcsr_mask & (1<<6) is doing. It's testing if bit 6 is set - ie denormals-are-zero mode is supported.

So if denormals-are-zero mode is supported, then _flags is or'd with HasDenormalsAreZero to indicate that this mode is supported.

OK. So we know what this code is doing. We need to get the value of MXCSR_MASK.

In all three versions of the FXSAVE map, the MXCSR_MASK is located at offset 28.

So I think you can just use _fxsave() - as the other info which is different depends upon mode etc isn't used.

Try it and see what you get.